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Which risk during integrated circuit fabrication increases when deposited polysilicon has high crystalline lattice defect density?

A)Increased electron mobility degradation over time
B)Enhanced dopant diffusion along grain boundaries
C)Reduced CMOS transistor threshold voltage mismatch
D)Elevated resistance of metal interconnect layers

💡 Explanation

Enhanced dopant profile diffusion increases primarily because of the grain boundary diffusion mechanism. High vacancy concentration results in more paths for dopant atoms to move, therefore enhanced diffusion rather than reduced mobility or increased transistor mismatch, which relate more to trapping.

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