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Which risk increases significantly when parasitic capacitance couples digital circuit clock signal to sensitive analog components?

A)Increased circuit settling time
B)Reduced current consumption in logic gates
C)Operational amplifier performance degradation
D)Destructive device latch-up

💡 Explanation

When digital signals couple through parasitic capacitance to analog sections, unwanted noise injection results because rapid signal changes capacitively couple, disturbing sensitive bias points. Therefore op-amp performance degrades, rather than faster settling, reduced current, or latch-up, which require other specific circuit conditions and mechanisms.

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